The present invention relates generally to semiconductor device manufacturing and, more particularly, to a structure and method for post silicide testing in replacement high-k metal gate (HKMG) technologies.
In standard complementary metal oxide semiconductor (CMOS) devices, polysilicon is typically used as the gate material. The technology of fabricating CMOS devices using polysilicon gates has been in a constant state of development, and is now widely used in the semiconductor industry. One advantage of using polysilicon gates is that they can sustain high temperatures. However, there are also some problems associated with using a polysilicon gate. For example, due to the poly-depletion effect, polysilicon gates commonly used in CMOS devices are becoming a gating factor in chip performance for channel lengths of 0.1 micron and below. Another problem with polysilicon gates is that the dopant material in the polysilicon gate (e.g., boron) can easily diffuse through the thin gate dielectric, causing further degradation of the device performance. Thus, one proposed way of improving the performance of sub-micron transistors is to use metal gates in place of conventional polysilicon gates, particularly with the advent of high-k gate dielectric materials.
In both traditional polysilicon gate structures and HKMG structures, post-silicide (PS) testing is used to test for faults such as, for example, opens and shorts within the gate conductor structure. Typically, a test device used for PS testing will include probe pads that are also formed from the gate electrode conductor material, and at the same device level as the gate structures (i.e., at the gate conductor or PC level). Although such test structures are suitable for PS testing in HKMG technology using a gate first integration scheme, they are not suitable for PS testing in HKMG technology using a gate last integration scheme. Since a gate last integration scheme initially entails forming a dummy gate structure (that is later removed to make way for the actual HKMG structure), only the active area (Rx) level shapes are exposed at the point of initial silicide formation. That is, the PC test probe pads are covered with an insulator material, thus rendering them unsuitable for electrical probing at this point in the manufacturing process.